Earlier this week Cadence announced that it worked with ARM to develop an implementation methodology for the recently announced, high-end ARM Cortex-A15 processor core, code-named Eagle. The ARM Cortex-A15 processor core has an expanded 40-bit (1Tbyte) memory address space (called Large Physical Address Extensions, LPAE), parity and ECC built into the processor’s cache controllers for both the L1 (32Kbytes of instruction and 32Kbytes of data per processor core) and L2 (maximum size = 4 Mbytes, shared among as many as four processor cores) caches, an AMBA 4 AXI Coherency Extensions (ACE) interface port, and hardware support for multicore designs and virtualization. According to the specification page, the ARM Cortex-A15 processor supports coherent multiprocessing using as many as four closely connected CPUs and supports multiple SMP (symmetric multiprocessing) clusters connected via the AMBA 4 interconnect fabric. The processor core’s virtualization capabilities involve “hardware support for data management and arbitration, whereby multiple software environments and their applications are able to simultaneously access the system capabilities” according to the online specification page. These are truly the specs of an apps-driven processor core.
ARM rolled out the new Cortex-A15 processor core earlier this month at an event held in San Francisco. At that time, ARM announced that the Cortex-A15 processor had been designed in conjunction with the 32nm and 28nm production process technology nodes being developed by IBM, GlobalFoundries, and Samsung. There was also mention during this announcement of a 2.5GHz maximum clock rate for the Cortex-A15 processor at the 28nm technology node. According to an article in EETimes, three of ARM’s silicon partners—Samsung, STMicroelectronics, and TI—will be the first to offer parts based on the ARM Cortex-A15 IP core. TI also participated with ARM and Cadence in this week’s related announcement.
For its part, Cadence supplied an optimized implementation methodology to ARM that enabled component vendors to gain early access to the ARM Cortex-A15 processor so that they could start early SoC development. Smooth implementation and integration of IP cores into SoC designs and streamlined conversion of those designs into silicon are bedrock concepts behind the EDA360 vision. By working closely with ARM during the development of the Cortex-A15 processor, Cadence has allowed the initial semiconductor vendors to more easily incorporate this advanced processor core into their SoC designs.
In July, Cadence announced collaboration with ARM to develop an optimized System Realization solution for ARM processors that will enable an end-to-end flow including a full set of interoperable tools, ARM processor and physical IP, services and methodology from embedded Linux to GDSII. Applications-driven System Realization is the topmost layer in the EDA360 vision, which posits an application-driven approach to ease the hardware/software integration issues currently hampering the smooth and rapid development of complete hardware/software platforms ready for applications development.
